The present invention is directed, in general, to semiconductor devices and, more specifically, to a semiconductor device having interdigitated electrodes over a well that is doped opposite to a substrate in which the well is formed.
As is well known, an EEPROM (electrically erasable programmable read-only memory) is user-modifiable read-only memory that can be erased and reprogrammed repeatedly through the application of higher than normal electrical voltage. In general, EEPROM cells have proven to be a reliable and versatile form of nonvolatile reprogrammable memory.
FIG. 1 illustrates a conventional EEPROM device 100. The EEPROM includes a doped substrate 110 having an oxide layer 120 thereon. A polysilicon floating gate 130 is located over the oxide layer 120 and serves as both the gate of a transistor 140 and an electrode of the EEPROM. A control gate 150 is located over the floating gate 130 and separated therefrom by a dielectric layer 160.
Despite the success of EEPROM cells as a reliable and versatile form of nonvolatile reprogrammable memory, conventional EEPROM devices have their drawbacks. For example, the additional process steps required to form the second polysilicon or other conductive material layer comprising the control gate (150) add significant cost and time in fabricating the devices. Moreover, additional production costs are incurred when the process for manufacturing the EEPROMs can not be easily integrated with existing processes. Faced with ever increasing demands for smaller devices, higher yields at lower cost, and reduced production times, these additional processing steps are undesirable.
Previous attempts to alleviate these disadvantages included forming coplanar floating and control gates (130, 150) such that both gates could be formed in a single deposition step of the manufacturing process. However, while the resulting structure required fewer processing steps, these xe2x80x9csingle polyxe2x80x9d EEPROM devices consumed large areas of the manufacturing wafer or die on which they were formed. This significantly increased area requirements and, therefore, limited the number of EEPROM devices fabricated on each die and increased the cost thereof. Thus, in addition to integration issues, EEPROM designers also face ever-increasing demands to decrease EEPROM surface area requirements.
Yet another issue that must be considered in addressing EEPROM manufacturing integration issues and decreasing EEPROM surface area requirements is maintaining an adequate coupling ratio. The coupling ratio (Cr) is given by the equation:
Cr=Ccgxe2x80x94fq/(Ccgxe2x80x94gf+Cfgxe2x80x94sub)xe2x80x83xe2x80x83(1)
where Ccgxe2x80x94fg is the capacitance formed by the control gate of the EEPROM cell and the floating gate, and Cfgxe2x80x94sub is the capacitance formed by the floating gate and the substrate thereunder.
The coupling ratio Cr may also be given by the equation:
Cr=Vfg/Vcgxe2x80x83xe2x80x83(2)
where Vfg is the operating voltage of the floating gate and Vcg is the operating voltage of the control gate. The operating voltage required at the control gate Vcg to obtain the desired floating gate voltage is also known as the programming and/or erasure voltage. Typically, EEPROMs are designed to have a predetermined floating gate operating voltage Vfg. However, the voltage on the control gate Vcg depends on the coupling ratio Cr of the EEPROM device. It is highly desirable to keep the Vcg as low as possible to achieve robust performance and to keep the overall voltage requirements for the device as low as possible.
However, in view of Equation (2), an excessively small coupling ratio Cr arising from decreased size or simplified integration requires an increased control gate voltage Vcg. Moreover, in view of Equation (1), any excessive capacitance of Cfgxe2x80x94sub decreases the coupling ratio Cr such that, again, an increased control gate voltage Vcg is required in order to maintain the preferred floating gate voltage Vfg. Unfortunately, past attempts to simplify EEPROM manufacturing integration with CMOS integration, or to decrease surface area required of individual EEPROM cells, have exhibited a substantial Cfgxe2x80x94sub, that disadvantageously decreased the coupling ratio Cr and increased control gate voltage Vcg requirements, which as discussed above is a less than desirable design choice.
Accordingly, what is needed in the art is a semiconductor device that does not suffer from the deficiencies found in the prior art.
To address the above-discussed deficiencies of the prior art, the present invention provides a semiconductor device comprising a semiconductor substrate having a well located therein and a first dielectric located over the well. The semiconductor substrate is doped with a first type dopant, and the well is doped with a second type dopant opposite to that of the first type dopant. The semiconductor device also comprises interdigitated first and second electrodes, wherein at least the first electrodes are located over the well and first dielectric. A second dielectric may be located between the first and second electrodes.
In another embodiment, the present invention provides an integrated circuit device comprising a transistor formed at least partially within a semiconductor substrate, a memory cell, and interconnects connecting the transistor and memory cell to form an integrated circuit. The semiconductor substrate is doped with a first type dopant. The memory cell includes a well located in the semiconductor substrate and doped with a second type dopant opposite to that of the first type dopant. A dielectric is located over the semiconductor substrate, and a floating gate is located over the dielectric and the well, wherein the floating gate is configured to form a series capacitance between the floating gate and the semiconductor substrate. This embodiment further includes a control gate that is located over the dielectric and that is substantially coplanar with and laterally offset from the floating gate, wherein the control gate is configured to form a capacitance between the control gate and the floating gate.
In yet another embodiment the present invention provides a method of manufacturing a semiconductor device, the method comprising locating a well in a semiconductor substrate doped with a first type dopant, wherein the well is doped with a second type dopant opposite to that of the first type dopant. The method also comprises locating a first dielectric over the well, forming interdigitated first and second electrodes, and positioning a second dielectric between the first and second electrodes. When forming the interdigitated first and second electrodes, at least the first electrodes are formed over the dielectric and the well.
The foregoing has outlined features of the present invention such that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present invention.